Ionized PVD has been utilized in semiconductor processing for metallization and interconnects, and appears promising for extension to submicron technology. In the metallization of high aspect ratio (HAR) via holes and trenches on semiconductor wafers, it has been considered important that the barrier layer and the seed layer have good sidewall and bottom coverage across the wafer. Ionized PVD deposition is used for barrier and seed layer metallization in advanced integrated circuit (IC) wafers, and has provided good sidewall and bottom coverage in via and trench structures. Requirements nonetheless become more critical as the geometries shrink and as the via dimensions go below 0.15 micrometers.
It is highly desirable to have an ionized PVD process where bottom and sidewall coverage are well balanced and overhang is minimized when features are small. To achieve this, the sequential deposition and etch processes have been proposed previously in U.S. Pat. No. 6,100,200 (Van Buskirk, et al.), however, at described temperatures the process would result in total agglomeration of Cu seed layers, overhang and closure of via and trenches with large islands of Cu and discontinuous Cu layers. Reduced temperature requires low power sputtering conditions that would put severe deposition rate and throughput limitations on such a process. Another limitation would occur when processing wafers in independent deposition and etch systems. Transferring the wafer between an etch chamber to a separate deposition chamber or between an etch station to a distinct deposition station within the same module has disadvantages both from cost-of-process and quality-of-process points of view.
In U.S. Pat. No. 4,999,096 (Nikei, et al.) a method of and apparatus for sputtering by sequential deposition and etching in the same chamber is disclosed. However, this configuration has a significant disadvantage in that the internal coil is a source of contamination of the film being deposited or etched on the substrate. Furthermore, the suggestions of Nikei, et al., would result in non-uniform plasma generation and non-uniform etching of the substrate, and in the sequential etching and deposition process, both steps are not uniform across the wafer so as to result in a uniformly processed wafer at the end of the process.
U.S. Pat. No. 6,274,008 discusses an integrated copper fill process where a simultaneous clean-deposit step is carried out, using copper ions to clean and/or etch the bottom of via structures before the copper seed layer is deposited.
Accordingly, there is a need in iPVD particularly to improve barrier layer and seed layer sidewall and bottom coverage across the wafer, particularly where feature dimensions are below 0.15 micrometers.